The typical semiconductor memory array comprises many hundreds or thousands of individual memory cells arranged in a orthogonal pattern of columns and rows on a chip. A bit line conductor connects all of the cells in each column and conducts signals to the cells in the column for the purpose of writing data to a cell or conducts signals from the cells in the column to read data from a cell. A word line conductor connects all of the cells in a horizontal row of the array and conducts a signal to activate the cells in the row. When it is desired to access a particular cell for a data read or a data write operation, the cells in the horizontal row which include the particular cell are activated by a signal on the word line conductor, and a signal is applied to or read from a bit line conductor of the column which includes the particular cell. Thus, only the particular cell at the intersection of the word and bit lines is thereby accessed.
When a data read operation occurs, a sense amplifier is connected to each bit line in the column which includes the particular accessed cell. The accessed cell supplies a relatively low level signal indicative of the logical state of the cell, and the sense amplifier amplifies the signal to a more reliable level useable by other elements on the memory. When a data write operation occurs signals are applied to the bit line conductors in order to set the logical state of the particular accessed cell.
The memory cells are usually one of two common types. One common type of memory cell, typified by a static random access memory (SRAM) cell, provides a pair of output signals at complementary logic levels. Two bit line conductors are therefore connected to each cell in each column, and the complementary output signals are applied to the two bit line conductors. The relative difference between the two complementary bit line signals is usually relatively small, for example 0.3 volts. The relative levels of the two signals represents the logical state of the cell. A differential sense amplifier receives both complementary bit line signals at its input terminals, senses the relationship between the two complementary signals and amplifies this relatively small differential signal to a level representative of the logical state of the cell, or to a level which is easily further amplified to a level representative of the logical state of the cell.
The other common type of memory cell, typified by an electrically erasable and programmable read only memory (EEPROM) cell, provides only a single output signal on a single bit line. The logical state of the cell is represented by whether the cell conducts current when it is accessed, indicating one logical state, or whether the cell will not conduct current when it is accessed, indicating the other logical state. The sense amplifier, which is single ended in this situation because it receives only a single input current signal from the single bit line, senses whether the cell absorbs current or not when it is accessed, and supplies an output signal of an amplified level representative of the logical state of the cell.
Many EEPROM cells employ a non-volatile device to retain the logical state of the cell when the power is removed from the array. The non-volatile device of the cell controls whether or not current is conducted by the cell in the logical states. The non-volatile device used in some memory cells is a silicon nitride oxide semiconductor (SNOS) transistor. A memory nitride layer of the SNOS transistor holds a charge to provide the non-volatile characteristic of the SNOS transistor. The two logical states of the cell are represented by whether the memory nitride layer of the SNOS transistor is charged with a negative electrical change or a positive electrical charge. These two states of the SNOS transistor are commonly referred to as the programmed and erased states, and these two transistor states establish the logical states of the cell.
The current conductivity characteristics of a SNOS transistor are considerably different in the programmed and erased states. For example, the amount of current conducted at the beginning of life of the SNOS transistor may be about 100 microamperes in one state and almost nothing in the other state. Over time, however, the ability of the memory nitride layer to retain the charge diminishes, due to natural life time deterioration. The amount of current which the SNOS transistor is capable of conducting in one state at the beginning of its life, may be up to ten times greater than that current it is capable of conducting in the same state at the end of its life. At the end of the expected life of the SNOS transistor, the memory nitride layer is incapable of holding a sufficient charge to modify the conduction characteristics of the transistor sufficiently enough to enable the sense amplifier to reliably distinguish the two logical states of the cell.
If the sense amplifier cannot reliably sense a difference in current between the two logical states of the cell (no current being conducted, and a small current being conducted), data from the cell can no longer be reliably recalled and the cell has reached the end of its useful lifetime. The utility of a non-volatile memory which employs SNOS or similar devices whose output current degrade with time, is influenced by its ability to reliably recall the correct data state under end of life conditions. Similarly, any type of memory cell that is subject to variable output currents is subject to many of the same problems and concerns as are applicable memory cells employing SNOS transistors. It is therefore desireable to extend the ability of the memory array to successfully recall data for as long as possible in the case of degrading devices such as SNOS transistors and under circumstances where there are potentially significant variations in the output or bit line current from the cell for reasons other than those associated with SNOS transistors.
The length of the bit lines in a memory array may be significant, since the bit lines connect hundreds or thousands of cells in each column. The bit line capacitance increases with its length. Large bit line capacitance makes sensing the bit line current more difficult, because the bit line draws current to charge its capacitance and modifies the amount of current sensed by the sense amplifier. The bit line capacitance makes it more difficult to reliably sense whether the cell is conducting current or not.
The settling time or time delay required to allow the bit line capacitance to charge or discharge before an accurate signal level representative of the logical state of the cell is available, increases the access time associated with the memory. The access time is that total amount of time required after the memory address signals are applied, for accessing a particular cell before the signal representative of the logical state of the cell is reliably presented. With most modern computer systems, increased access times are undesirable because they delay the data processing functions.
It is against this abbreviated summary of considerations that the present invention of improvements in single ended sense amplifiers has evolved.